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timing controller for ccd camera description the cxD2463R generates the sync signals for timing control and back end signal processing in a ccd camera system using a 510h or 760h black- and-white ccd image sensor. features built-in sync signal generation function built-in electronic iris (electronic shutter) function supports low-speed limiter for electronic iris supports external synchronization (line-lock, vreset + hpll) supports automatic external sync discrimination window pulse output for backlight compensation built-in v driver applications surveillance camera door phone camera structure silicon gate cmos ic applicable ccd image sensors type 1/2, 760h black-and-white ccd (eia/ccir) type 1/3, 510/760h black-and-white ccd (eia/ccir) type 1/4, 510/760h black-and-white ccd (eia/ccir) absolute maximum ratings supply voltage v dd , av dd v ss ?0.5 to v ss + 7.0 v supply voltage v ss vl ?0.5 to vl + 26.0 v supply voltage vh vl ?0.5 to vl + 26.0 v supply voltage vm vl ?0.5 to vl + 26.0 v input voltage v i v ss ?0.5 to v dd + 0.5 v output voltage v o v ss ?0.5 to v dd + 0.5 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage 1 v dd , av dd 4.75 to 5.25 v supply voltage 3 vh 14.55 to 15.45 v supply voltage 4 vl ?.0 to ?.0 v supply voltage 5 vm 0 v operating temperature topr ?0 to +75 ? base oscillation 1212f h (eia: 19.0699mhz) (ccir: 18.9375mhz) 1820f h (eia: 28.6364mhz) 1816f h (ccir: 28.375mhz) ?1 e98930b9x sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxD2463R 48 pin lqfp (plastic)
? 2 cxD2463R no signal detection circuit vd detection circuit sync discrimination circuit gate hv-pll selector lcin comp evd ehd/sync ext hvdet vd hd eia v dd 1 v dd 2 v ss 1 v ss 2 test lcout cki ccd av ss h1 h2 av dd rg shp shd v1 v2 v3 v4 vl vm sub vh sync cblk clp1 clp2 blc blcw2 blcw1 cv ss irin/ed1 spdnv/ed2 vreg cv dd spupv/ed0 1/2 1/606 1/910 1/908 tg/ssg reset gen iris/shutter ck gen counter eshut2 eshut1 rst test circuit selector decode up/down adder gate vd ihd ivd eia hd 40 39 41 42 28 47 45 46 44 48 31 30 6 3 4 2 8 1 7 5 25 26 23 24 15 17 18 12 13 11 10 9 20 21 29 22 32 16 43 19 27 36 35 33 34 38 37 14 1/525 1/625 sync sep v driver decoder hv-pll selector block diagram
? 3 cxD2463R pin configuration (top view) 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 i r i n / e d 1 c v s s b l c v s s 1 b l c w 1 b l c w 2 v d d 1 e s h u t 2 e s h u t 1 t e s t c l p 1 c l p 2 s y n c c b l k e i a c c d r s t s h d s h p v s s 2 h v d e t e x t v d h d s p d n v / e d 2 s p u p v / e d 0 v r e g c v d d v l s u b v 1 v h v 3 v 2 v 4 v m r g a v s s h 2 h 1 a v d d v d d 2 c k i l c o u t l c i n c o m p e h d / s y n c e v d pin description pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 vm v4 v2 v3 vh v1 sub vl cv dd vreg spupv/ed0 spdnv/ed2 irin/ed1 cv ss o o o o o i i i power supply (gnd for v driver) pulse output for ccd vertical register drive pulse output for ccd vertical register drive pulse output for ccd vertical register drive power supply (positive power supply for v driver) pulse output for ccd vertical register drive ccd discharge pulse output power supply (negative power supply for v driver) power supply (for comparator) bias current supply for comparator shutter speed up reference voltage/shutter speed setting shutter speed down reference voltage/shutter speed setting iris signal input/shutter speed setting gnd (for comparator) symbol i/o description
? 4 cxD2463R pin no. 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 blc v ss 1 blcw1 blcw2 v dd 1 eshut2 eshut1 test clp1 clp2 sync cblk eia ccd rst shd shp v ss 2 hvdet ext vd hd evd ehd/sync comp lcin lcout cki v dd 2 av dd h1 h2 av ss rg o i i i i i o o o o i i i o o o o o o i i o i o i o o o window pulse output for backlight compensation gnd window select 1 for backlight compensation (with pull-down resistor) window select 2 for backlight compensation (with pull-down resistor) power supply sub pulse control (with pull-down resistor) sub pulse control (with pull-down resistor) fixed low (with pull-down resistor) clamp pulse output clamp pulse output composite sync output composite blanking output low: eia, high: ccir (with pull-down resistor) low: 510h, high: 760h (with pull-down resistor) reset (low reset). always input reset pulse after power-on. data sample-and-hold pulse precharge level sample-and-hold pulse gnd horizontal pll/vertical pll discrimination signal high: vertical pll, low: horizontal pll external sync/internal sync discrimination signal high: external sync, low: internal sync vertical drive output horizontal drive output vertical drive signal input (with pull-up resistor) horizontal drive signal input/composite sync input (with pull-up resistor) comparator output inverter input for oscillation inverter output for oscillation 2mck input power supply power supply (for h1, h2, and rg) h1 clock output for ccd horizontal register drive h2 clock output for ccd horizontal register drive gnd (for h1, h2, and rg) reset gate pulse output symbol i/o description
? 5 cxD2463R electrical characteristics 1) dc characteristics (v dd = 5v 0.25v, topr = ?0 to +75 c) item v dd v ih 1 v il 1 v ih 2 v il 2 v in 3 v in 4 v oh 1 v ol 1 v oh 2 v ol 2 v oh 3 v ol 3 v oh 4 v ol 4 v oh 5 v ol 5 v oh 6 v ol 6 v oh 7 v ol 7 r fe 1 r fe 2 r pu r rd i vm i vl i vh i oh = ?.0ma i ol = 8.0ma i oh = ?.9ma i ol = 3.0ma i oh = ?7.4ma i ol = 12.0ma i oh = ?.0ma i ol = 4.0ma i oh = ?.0ma i ol = 10.0ma i oh = ?.2ma i ol = 5.0ma i oh = ?.0ma i ol = 5.4ma v in = v dd or v ss v in = v dd or v ss v il = 0v v ih = v dd av dd = 5v cv dd = 5v v dd 1 = 5v v dd 2 = 5v v l = ?.5v v h = 15v 4.75 0.7v dd 0.8v dd 2.0 v ss v dd ?0.8 v dd ?0.8 v dd ?0.8 v dd ?0.8 v m ? 0.25 v h ? 0.25 v h ? 0.25 250k 250k 20k 20k 5.0 1m 1m 50k 50k 24 1.9 0.8 5.25 0.3v dd 0.2v dd v dd v dd 0.4 0.4 0.4 0.4 v l + 0.25 v m + 0.25 v l + 0 .25 2.5m 2.5m 125k 125k v v v v v v v v v v v v v v v v v v v v v ma ma ma symbol conditions min. typ. max. unit supply voltage input voltage 1 (for input pins not listed below) input voltage 2 (pin 29) input voltage 3 (pins 11 and 12 in electronic iris mode) input voltage 4 (pin 13 in electronic iris mode) output voltage 1 (pins 15, 23, 24, 25, 26, 33, 34, 35 and 36) output voltage 2 (pins 30, 31 and 48) output voltage 3 (pins 45 and 46) output voltage 4 (pin 39) output voltage 5 (pins 2, 3, 4 and 6) output voltage 6 (pins 4 and 6 (sg)) output voltage 7 (pin 7) feedback resistor 1 (pin 42) feedback resistor 2 (resistor between pins 40 and 41) pull-up resistor pull-down resistor current consumption * the typical power consumption is 148mw with the icx054bl load (in the normal operating state).
? 6 cxD2463R 2) input/output capacitance (v dd = v i = 0v, f m = 1mhz) item input pin capacitance output pin capacitance i/o pin capacitance c in c out c i/o 9 11 11 pf pf pf symbol min. typ. max. unit 3) comparator characteristics (v dd = 5v 0.25v, topr = ?0 to +75 c) item indefinite region vf 70 mv symbol min. typ. max. unit 4) power-on reset condition (within the recommended operating condition) item power-on reset period t wrst 35 ns symbol min. typ. max. unit note 1) input offset voltage and indefinite region the input offset voltage and indefinite region (region in which the comparator output is not set to high or low) shown in the figure below exist in the built-in comparator in this ic, so be careful when designing the external circuit. note 2) pins 11 and 12 in electronic iris mode make sure of pin 11 (spupv) < pin 12 (spdnv). 5 . 0 v g n d 7 0 m v 7 0 m v p i n s 1 1 a n d 1 2 ( s p u p v , s p d n v ) i n d e f i n i t e r e g i o n 4 . 7 5 v t w r s t 0 . 2 v d d v d d r s t
? 7 cxD2463R 1. electronic iris/electronic shutter function the electronic iris or electronic shutter can be selected by setting the following pins to different combinations of high and low. eshut1 pin 21 l h l h l l h h electronic iris without limiter electronic iris with limiter eia: 1/100 (s), ccir: 1/120 (s) electronic shutter mode sub pulse stopped eshut2 pin 20 operating mode symbol irin/ed1 spdnv/ed2 spupv/ed0 13 12 11 iris signal input shutter speed down reference voltage shutter speed up reference voltage pin no. function 1) electronic iris mode symbol spupv/ed0 irin/ed1 spdnv/ed2 shutter speed 11 13 12 h h h eia: 1/100 ccir: 1/120 l h h 1/250 h l h 1/500 l l h 1/1000 h h l 1/2000 l h l 1/5000 h l l 1/10000 l l l 1/100000 pin no. mode 2) electronic shutter mode
? 8 cxD2463R 2. backlighting correction function the cxD2463R has a function to output the window pulse for backlight compensation. the backlight compensation pulse is output from blc (pin 15) in the following range according to the high/low combination of blcw1 (pin 17) and blcw2 (pin 18). window type for different pin combinations window type full-screen photometry bottom emphasis photometry center emphasis photometry bottom + center emphasis photometry l h l h l l h h blcw1 (pin 17) blcw2 (pin 18) example of basic circuit configuration i r i s c o m p a r a t o r i r i s w i n d o w s w i t c h a g c w i n d o w s w i t c h i r i n / e d 1 1 3 b l c 3 . 9 k 1 0 k 3 9 k + 5 v 1 0 0 k 1 0 i r i s o p + d e t o u t 1 k 1 0 k 1 0 0 k 1 0 1 0 k 1 0 k c x d 2 4 6 3 r c x a 1 3 1 0 a q 1 5 2 7 1 9 1 3 f u l l - s c r e e n p h o t o m e t r y c e n t e r e m p h a s i s p h o t o m e t r y b o t t o m e m p h a s i s p h o t o m e t r y b o t t o m + c e n t e r e m p h a s i s p h o t o m e t r y
? 9 cxD2463R 1) window pulse timing charts ?eia mode/vertical direction timing (1) full-screen photometry v d h d b l c 2 0 h d 2 0 . 5 h d 0 . 5 h d (2) center emphasis photometry v d h d b l c 1 8 1 h d 1 0 1 h d 1 8 1 . 5 h d 1 0 1 . 5 h d (3) bottom emphasis photometry v d h d b l c 1 8 1 h d 1 8 1 . 5 h d 0 . 5 h d
? 10 cxD2463R ?eia mode/horizontal direction timing (1) bottom emphasis photometry and full-screen photometry h d m c k b l c x 1 x 2 x1 510h 760h 510h 760h 104mck 154mck 3mck 22mck x2 (2) center emphasis photometry h d m c k b l c x 1 x 2 x1 510h 760h 510h 760h 272mck 407mck 167mck 252mck x2
? 11 cxD2463R ?ccir mode/vertical direction timing (1) full-screen photometry v d h d b l c 2 5 h d 2 5 . 5 h d 0 . 5 h d (2) center emphasis photometry v d h d b l c 2 1 6 h d 1 2 1 h d 2 1 6 . 5 h d 1 2 1 . 5 h d (3) bottom emphasis photometry v d h d b l c 2 1 6 h d 2 1 6 . 5 h d 0 . 5 h d
? 12 cxD2463R ?ccir mode/horizontal direction timing (1) bottom emphasis photometry and full-screen photometry h d m c k b l c x 1 x 2 x1 510h 760h 510h 760h 114mck 169mck 3mck 22mck x2 (2) center emphasis photometry h d m c k b l c x 1 x 2 x1 510h 760h 510h 760h 279mck 416mck 164mck 246mck x2
? 13 cxD2463R 3. external sync function the cxD2463R supports the three modes of line-lock, vreset + hpll (vd and hd inputs), and vreset + hpll (sync input) as the external sync functions. each mode is automatically switched according to the combination of signals input to ehd/sync (pin 38) and evd (pin 37). 1) automatic external sync discrimination i/o i i o o ehd/sync evd hvdet ext 38 37 33 34 hd no signal l l int no signal vd h h ll hd vd l h vreset + hpll sync hd after sync separation l h vreset + hpll no signal no signal l l int symbol pin no. ehd/sync and evd pins signal input state and hvdet and ext pins discrimination results mode if unspecified signals are input for the external signals given above, there may be recognition errors. 2) ll (line-lock) mode when the v sync clock is externally input to evd (pin 37), the result of comparing the falling edge of the clock and the falling edge of the internal vd is output from comp (pin 39). the output polarity is compatible with the active filter. e x t - v d ( p i n 3 7 ) i n t - v d ( p i n 3 5 ) c o m p ( p i n 3 9 ) h i g h i m p e d a n c e s t a t e
? 14 cxD2463R 3) vreset + hpll (vd and hd inputs) mode when the hd cycle clock is externally input to ehd/sync (pin 38) and the v cycle clock is externally input to the evd (pin 37), the cxD2463R sync signal is output as shown below based on the phase difference between these signals. similar to line-lock mode, the result of comparing the phase of the falling edges of the hd cycle clock input to pin 38 and the cxD2463R internal hd is output from comp (pin 39). the pll is applied using this signal. similar to line-lock mode, the polarity of the comp (pin 39) output is compatible with the active filter. the phase of the hd falling edge can be shifted up to 1/4h with respect to the falling edge of the master vd (ext- vd). ?eia/odd (1) ext-vd and ext-hd have the same phase. 1 / 4 h 1 / 4 h e x t - v d ( p i n 3 7 i n p u t ) e x t - h d ( p i n 3 8 i n p u t ) v d ( p i n 3 5 o u t p u t ) h d ( p i n 3 6 o u t p u t ) s y n c ( p i n 2 5 o u t p u t ) (2) ext-vd and ext-hd have the same phase to +1/4h. e x t - v d e x t - h d v d h d s y n c (3) ext-vd and ext-hd have the ?/4h to the same phase. e x t - v d e x t - h d v d h d s y n c
? 15 cxD2463R ?eia/even (1) ext-vd and ext-hd have the same phase. 1 / 4 h 1 / 4 h e x t - v d ( p i n 3 7 i n p u t ) e x t - h d ( p i n 3 8 i n p u t ) v d ( p i n 3 5 o u t p u t ) h d ( p i n 3 6 o u t p u t ) s y n c ( p i n 2 5 o u t p u t ) (2) ext-vd and ext-hd have the same phase to +1/4h. e x t - v d e x t - h d v d h d s y n c (3) ext-vd and ext-hd have the same phase to ?/4h. e x t - v d e x t - h d v d h d s y n c
? 16 cxD2463R ?ccir/odd (1) ext-vd and ext-hd have the same phase. 1 / 4 h 1 / 4 h e x t - v d ( p i n 3 7 i n p u t ) e x t - h d ( p i n 3 8 i n p u t ) v d ( p i n 3 5 o u t p u t ) h d ( p i n 3 6 o u t p u t ) s y n c ( p i n 2 5 o u t p u t ) (2) ext-vd and ext-hd have the same phase to +1/4h. e x t - v d e x t - h d v d h d s y n c (3) ext-vd and ext-hd have the same phase to ?/4h. e x t - v d e x t - h d v d h d s y n c
? 17 cxD2463R ?ccir/even (1) ext-vd and ext-hd have the same phase. 1 / 4 h 1 / 4 h e x t - v d ( p i n 3 7 i n p u t ) e x t - h d ( p i n 3 8 i n p u t ) v d ( p i n 3 5 o u t p u t ) h d ( p i n 3 6 o u t p u t ) s y n c ( p i n 2 5 o u t p u t ) (2) ext-vd and ext-hd have the same phase to +1/4h. e x t - v d e x t - h d v d h d s y n c (3) ext-vd and ext-hd have the same phase to ?/4h. e x t - v d e x t - h d v d h d s y n c
? 18 cxD2463R 4) vreset + hpll (sync input) mode when the specified sync signal is externally input to ehd/sync (pin 38), the ext-hd separated from this sync signal is output from hd (pin 36). this signal is input through the shifter to evd (pin 37). at this time, the cxD2463R sync signal is output as shown below based on the amount by which ext-hd is shifted. (the phase can be shifted up to 1/2h with respect to the falling edge of ext-hd.) comp (pin 39) outputs the result of comparing the phase of the falling edge of the shifted ext-hd (signal input to pin 37) and the falling edge of the cxD2463R internal hd. the polarity is compatible with the active filter. ?eia/odd e x t - h d ( p i n 3 6 o u t p u t ) ( 1 ) s a m e p h a s e ( 2 ) d e l a y e d p h a s e e x t - v d ( g e n e r a t e d i n s i d e t h e c x d 2 4 6 3 r ) h d ( g e n e r a t e d i n s i d e t h e c x d 2 4 6 3 r ) e x t - s y n c ( p i n 3 8 i n p u t ) * s f t - h d ( 1 ) t o ( 3 ) a r e t h e s i g n a l s a f t e r s h i f t i n g e x t - h d . 1 / 2 h 1 / 2 h v d ( p i n 3 5 o u t p u t ) s f t - h d ( 1 ) ( p i n 3 7 i n p u t ) s f t - h d ( 2 ) v d h d s y n c ( 3 ) a d v a n c e d p h a s e s f t - h d ( 3 ) v d h d s y n c s y n c ( p i n 2 5 o u t p u t )
? 19 cxD2463R ?eia/even e x t - h d ( p i n 3 6 o u t p u t ) ( 1 ) s a m e p h a s e ( 2 ) d e l a y e d p h a s e e x t - v d ( g e n e r a t e d i n s i d e t h e c x d 2 4 6 3 r ) h d ( g e n e r a t e d i n s i d e t h e c x d 2 4 6 3 r ) e x t - s y n c ( p i n 3 8 i n p u t ) 1 / 2 h 1 / 2 h v d ( p i n 3 5 o u t p u t ) s f t - h d ( 1 ) ( p i n 3 7 i n p u t ) s f t - h d ( 2 ) v d h d s y n c ( 3 ) a d v a n c e d p h a s e s f t - h d ( 3 ) v d h d s y n c s y n c ( p i n 2 5 o u t p u t )
? 20 cxD2463R ?ccir/odd e x t - h d ( p i n 3 6 o u t p u t ) ( 1 ) s a m e p h a s e ( 2 ) d e l a y e d p h a s e e x t - v d ( g e n e r a t e d i n s i d e t h e c x d 2 4 6 3 r ) h d ( g e n e r a t e d i n s i d e t h e c x d 2 4 6 3 r ) e x t - s y n c ( p i n 3 8 i n p u t ) 1 / 2 h 1 / 2 h v d ( p i n 3 5 o u t p u t ) s f t - h d ( 1 ) ( p i n 3 7 i n p u t ) s f t - h d ( 2 ) v d h d s y n c ( 3 ) a d v a n c e d p h a s e s f t - h d ( 3 ) v d h d s y n c s y n c ( p i n 2 5 o u t p u t )
? 21 cxD2463R ?ccir/even e x t - h d ( p i n 3 6 o u t p u t ) ( 1 ) s a m e p h a s e ( 2 ) d e l a y e d p h a s e e x t - v d ( g e n e r a t e d i n s i d e t h e c x d 2 4 6 3 r ) h d ( g e n e r a t e d i n s i d e t h e c x d 2 4 6 3 r ) e x t - s y n c ( p i n 3 8 i n p u t ) 1 / 2 h 1 / 2 h v d ( p i n 3 5 o u t p u t ) s f t - h d ( 1 ) ( p i n 3 7 i n p u t ) s f t - h d ( 2 ) v d h d s y n c ( 3 ) a d v a n c e d p h a s e s f t - h d ( 3 ) v d h d s y n c s y n c ( p i n 2 5 o u t p u t )
? 22 cxD2463R h d f i e l d . o f i e l d . e v d s y n c b l k v 1 v 2 v 3 v 4 5 1 0 h c c d o u t 7 6 0 h c c d o u t c l p 1 1 3 2 4 1 3 2 4 4 9 2 4 9 3 4 9 2 4 9 3 c l p 2 9 h 2 0 h 4 9 4 h d f i e l d . e f i e l d . o v d s y n c b l k v 1 v 2 v 3 v 4 5 1 0 h c c d o u t 7 6 0 h c c d o u t c l p 1 4 9 1 2 4 9 3 4 9 2 1 3 1 3 2 4 9 3 4 9 4 c l p 2 9 h 2 0 h timing generator + sync generator block timing chart vertical direction eia (during 510h/760h ccd drive)
? 23 cxD2463R h d f i e l d . e f i e l d . o v d s y n c b l k v 1 v 2 v 3 v 4 5 1 0 h c c d o u t 5 8 1 5 8 2 5 8 3 2 1 3 7 . 5 h 2 5 h h d f i e l d . o f i e l d . e v d s y n c b l k 7 . 5 h 2 5 h 1 3 2 4 5 8 2 5 8 3 v 1 v 2 v 3 v 4 5 1 0 h c c d o u t c l p 1 c l p 2 c l p 1 c l p 2 timing generator + sync generator block timing chart vertical direction ccir (during 510h ccd drive)
? 24 cxD2463R h d f i e l d . e f i e l d . o v d s y n c b l k v 1 v 2 v 3 v 4 7 6 0 h c c d o u t 5 8 1 5 8 2 5 8 3 2 1 3 7 . 5 h 2 5 h h d f i e l d . o f i e l d . e v d s y n c b l k 7 . 5 h 2 5 h 1 2 5 8 2 5 8 3 v 1 v 2 v 3 v 4 7 6 0 h c c d o u t c l p 1 c l p 2 c l p 1 c l p 2 timing generator + sync generator block timing chart vertical direction ccir (during 760h ccd drive)
? 25 cxD2463R h d / b l k m c k ( i n t e r n a l c l o c k ) h 1 h 2 r g s h p s h d v 1 v 2 v 3 v 4 s u b h s y n c e q v s y n c v d c l p 1 c l p 2 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 0 4 m c k = 1 0 4 . 8 8 n s 5 9 7 9 2 6 8 0 9 4 5 0 3 2 6 2 4 4 5 6 2 6 6 8 3 8 7 2 5 5 5 9 1 4 3 6 1 4 1 4 2 3 7 timing generator + sync generator block timing chart horizontal direction eia (during 510h ccd drive)
? 26 cxD2463R h d / b l k m c k ( i n t e r n a l c l o c k ) h 1 h 2 r g s h p s h d v 1 v 2 v 3 v 4 s u b h s y n c e q v s y n c v d c l p 1 c l p 2 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 1 4 5 9 8 4 3 1 8 5 9 9 5 5 3 7 6 7 4 9 6 1 3 1 7 3 4 3 7 7 6 0 5 9 1 4 3 6 1 4 1 4 2 3 7 m c k = 1 0 5 . 6 1 n s timing generator + sync generator block timing chart horizontal direction ccir (during 510h ccd drive)
? 27 cxD2463R 0 1 0 2 0 9 0 8 0 1 4 0 1 5 0 1 6 0 1 7 0 1 0 0 6 0 5 0 4 0 3 0 7 0 1 1 0 1 2 0 1 3 0 1 5 4 9 0 4 0 1 1 8 3 6 1 2 1 4 0 1 1 9 7 6 4 9 9 4 6 7 8 5 4 0 1 0 3 5 8 1 0 8 8 5 9 0 2 2 5 6 2 2 2 2 h d / b l k m c k ( i n t e r n a l c l o c k ) h 1 h 2 r g s h p s h d v 1 v 2 v 3 v 4 s u b h s y n c e q v s y n c v d c l p 1 c l p 2 m c k = 6 9 . 8 4 n s timing generator + sync generator block timing chart horizontal direction eia (during 760h ccd drive)
? 28 cxD2463R 0 1 0 2 0 9 0 8 0 1 4 0 1 5 0 1 6 0 1 7 0 1 0 0 6 0 5 0 4 0 3 0 7 0 1 1 0 1 2 0 1 3 0 1 6 9 9 0 4 0 1 3 2 3 6 1 2 1 5 4 8 4 5 1 1 0 6 7 3 9 5 4 0 1 1 7 6 2 1 2 2 9 5 9 0 2 2 5 6 2 2 2 2 h d / b l k m c k ( i n t e r n a l c l o c k ) h 1 h 2 r g s h p s h d v 1 v 2 v 3 v 4 s u b h s y n c e q v s y n c v d c l p 1 c l p 2 m c k = 7 0 . 4 8 n s 1 3 3 timing generator + sync generator block timing chart horizontal direction ccir (during 760h ccd drive)
? 29 cxD2463R h d e : 2 . 5 1 s c : 2 . 5 3 s ( 2 4 c k ) v 1 o d d v 2 v 3 v 4 v 1 e v e n v 2 v 3 v 4 e : 1 . 5 7 s c : 1 . 5 8 s ( 1 5 c k ) e : 1 . 9 9 s c : 2 . 0 0 s ( 1 9 c k ) e : e i a 1 c k = 1 0 4 . 8 8 n s c : c c i r 1 c k = 1 0 5 . 6 1 n s e : 3 8 . 3 8 s c : 3 8 . 6 5 s ( 3 6 6 c k ) ( 1 2 c k ) e : 1 . 2 6 s c : 1 . 2 7 s ( 3 c k ) e : 0 . 3 2 s c : 0 . 3 2 s timing generator + sync generator block timing chart charge readout timing field accumulation (during 510h ccd drive)
? 30 cxD2463R h d e : 2 . 5 1 s c : 2 . 5 4 s ( 3 6 c k ) v 1 o d d v 2 v 3 v 4 v 1 e v e n v 2 v 3 v 4 e : 2 . 5 1 s c : 2 . 5 4 s ( 3 6 c k ) e : 2 . 5 1 s c : 2 . 5 4 s ( 3 6 c k ) e : e i a 1 c k = 6 9 . 8 4 n s c : c c i r 1 c k = 7 0 . 4 8 n s e : 4 0 . 5 6 s c : 4 0 . 9 5 s ( 5 8 1 c k ) ( 2 3 c k ) e : 1 . 6 1 s c : 1 . 6 2 s ( 3 c k ) e : 0 . 2 1 s c : 0 . 2 1 s timing generator + sync generator block timing chart charge readout timing field accumulation (during 760h ccd drive)
? 31 cxD2463R h d 3 1 . 7 8 s ( 3 0 3 c k ) 1 . 4 7 s ( 1 4 c k ) 1 / 2 h e i a h s y n c e q v s y n c b l k ( h d ) b l k ( o d d ) b l k ( e v e n ) v d ( e v e n ) v d ( o d d ) 6 . 1 9 s ( 5 9 c k ) 4 . 7 2 s ( 4 5 c k ) 2 . 3 0 s ( 2 2 c k ) 4 . 7 2 s ( 4 5 c k ) 2 . 3 0 s ( 2 2 c k ) 1 . 4 7 s ( 1 4 c k ) 1 c k = 1 0 4 . 8 8 n s 4 . 7 2 s ( 4 5 c k ) 1 0 . 9 0 s ( 1 0 4 c k ) timing generator + sync generator block timing chart effective horizontal period (during 510h ccd drive)
? 32 cxD2463R h d 3 2 . 0 0 s ( 3 0 3 c k ) 1 . 4 8 s ( 1 4 c k ) 1 / 2 h c c i r h s y n c e q v s y n c b l k ( h d ) b l k ( o d d ) v d ( e v e n ) v d ( o d d ) b l k ( e v e n ) 6 . 2 3 s ( 5 9 c k ) 4 . 7 5 s ( 4 5 c k ) 2 . 3 0 s ( 2 2 c k ) 4 . 7 5 s ( 4 5 c k ) 2 . 3 0 s ( 2 2 c k ) 1 . 4 8 s ( 1 4 c k ) 1 c k = 1 0 5 . 6 1 n s 4 . 7 5 s ( 4 5 c k ) 1 2 . 0 4 s ( 1 1 4 c k ) timing generator + sync generator block timing chart effective horizontal period (during 510h ccd drive)
? 33 cxD2463R h d 3 1 . 7 8 s ( 4 5 5 c k ) 1 . 5 4 s ( 2 2 c k ) 1 / 2 h e i a h s y n c e q v s y n c b l k ( h d ) b l k ( o d d ) b l k ( e v e n ) v d ( e v e n ) v d ( o d d ) 6 . 2 9 s ( 9 0 c k ) 4 . 7 5 s ( 6 8 c k ) 2 . 3 7 s ( 3 4 c k ) 4 . 7 5 s ( 6 8 c k ) 2 . 3 7 s ( 3 4 c k ) 1 . 5 4 s ( 2 2 c k ) 1 c k = 6 9 . 8 4 n s 4 . 7 5 s ( 6 8 c k ) 1 0 . 7 6 s ( 1 5 4 c k ) timing generator + sync generator block timing chart effective horizontal period (during 760h ccd drive)
? 34 cxD2463R h d 3 2 . 0 0 s ( 4 5 4 c k ) 1 . 5 5 s ( 2 2 c k ) 1 / 2 h c c i r h s y n c e q v s y n c b l k ( h d ) b l k ( o d d ) v d ( e v e n ) v d ( o d d ) b l k ( e v e n ) 6 . 3 4 s ( 9 0 c k ) 4 . 7 9 s ( 6 8 c k ) 2 . 4 0 s ( 3 4 c k ) 4 . 7 9 s ( 6 8 c k ) 2 . 4 0 s ( 3 4 c k ) 1 . 5 5 s ( 2 2 c k ) 1 c k = 7 0 . 4 8 n s 4 . 7 9 s ( 6 8 c k ) 1 1 . 9 1 s ( 1 6 9 c k ) timing generator + sync generator block timing chart effective horizontal period (during 760h ccd drive)
? 35 cxD2463R h 1 h 2 r g c c d o u t m c k ( i n t e r n a l c l o c k ) s h p s h d high-speed phase timing chart for the timing generator block
? 36 cxD2463R v s u b a d j 3 6 k 5 0 k 5 0 k 1 0 k 3 . 9 k 1 0 0 + 5 v 1 0 0 1 0 k 1 0 v i d e o o u t c c d o u t 1 0 1 0 0 k 1 0 k 9 . 0 t o 8 . 0 v + 1 4 . 5 5 t o + 1 5 . 4 5 v r e s e t c i r c u i t h s h i f t e r r g a d j 1 0 0 0 p 1 0 p 1 0 k 1 0 k 1 0 k 1 0 0 k 1 0 0 0 p 1 m 0 . 0 1 s y n c i n 0 . 1 1 m 1 p 3 9 k c x a 1 3 1 0 a q c x d 2 4 6 3 r 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 2 5 3 0 2 7 2 4 2 0 2 1 2 9 4 5 1 0 h / 7 6 0 h b l a c k - a n d - w h i t e c c d application circuit ?sync input external synchronization ?electronic iris mode application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 37 cxD2463R s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n p l a t i n g 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e 4 8 p i n l q f p ( p l a s t i c ) 9 . 0 0 . 2 * 7 . 0 0 . 1 1 1 2 1 3 2 4 2 5 3 6 3 7 4 8 ( 0 . 2 2 ) 0 . 1 8 0 . 0 3 + 0 . 0 8 0 . 2 g l q f p - 4 8 p - l 0 1 l q f p 0 4 8 - p - 0 7 0 7 ( 8 . 0 ) 0 . 5 0 . 2 0 . 1 2 7 0 . 0 2 + 0 . 0 5 a 1 . 5 0 . 1 + 0 . 2 0 . 1 s o l d e r / p a l l a d i u m n o t e : d i m e n s i o n * d o e s n o t i n c l u d e m o l d p r o t r u s i o n . 0 . 1 0 . 1 0 . 5 0 . 2 0 t o 1 0 d e t a i l a 0 . 1 3 m 0 . 5 s s b d e t a i l b : s o l d e r ( 0 . 1 8 ) ( 0 . 1 2 7 ) d e t a i l b : p a l l a d i u m 0 . 1 2 7 0 . 0 4 0 . 1 8 0 . 0 3 + 0 . 0 8 0 . 1 2 7 0 . 0 2 + 0 . 0 5 0 . 1 8 0 . 0 3 package outline unit: mm

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